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ML7224-001
4Ch VoIP CODEC
 

Documents

»  PDF of this Data Sheet (2.68 MB) is available. ML7224-001.pdf

Description

The ML7224-001 is a VoIP codec that has speech codecs with four channels. These speech codecs support the PLC (Packet Loss Concealment) function, with the coding format selectable between G.711 (μ-law) and G.711 (A-law). The ML7224-001 is equipped with an echo canceller that supports a delay of 32 ms for each channel; it also has functions such as FSK generation, DTMF detection/generation, and tone detection/generation. The ML7224-001 is an LSI device best suited to add multichannel VoIP capability to a TA, router and others. Note that because this LSI device employs the method of downloading the DSP firmware from outside of the LSI to a built-in memory, it is capable of supporting functional expansion by changing the DSP firmware.

 

Features

»  Speech codecs (with 4 channels):
- Selectable between ITU-T G.711 (64 kbps) μ-law and A-law
- Supports ITU-T G.711 Appendix I compliant PLC (Packet Loss Concealment) function
»  Interface for transferring speech CODEC transmit/receive data:
- Selectable between FIFO buffer interface and PCM interface
»  FIFO buffer interface:
- Number of interfaces : 2 (one for CH0a/CH1a and the other for CH0b/CH1b)
- FIFO buffer size : CH0a/CH1a: 640 bytes, CH0b/CH1b: 640 bytes
- Frame/DMA (slave) interface can be selected
»  PCM interface
- Number of interfaces : 2 (one for CH0a/CH1a and the other for CH0b/CH1b)
- Serial transmission rate : 128 kHz to 2.048 MHz (fixed at 2.048 MHz during output)
- 1-time-slot bit width : Fixed to 16 bits
- Time slot assignment : A maximum of 16 slots can be assigned (when BCLK = 2.048 MHz)
- Input time slot selection : Arbitrary 4 slots maximum can be selected (for each block)
- Output time slot selection : Arbitrary 2 slots maximum can be selected (for each block)
»  Front-end interface
- Selectable between analog interface and PCM interface
»  Analog interface
- Number of interfaces : 4 with one input amplifier and one output amplifier incorporated for each channel (10 kΩ driving)
»  Echo canceller for 32 ms delay (One block installed per channel.)
»  DTMF detection function (One block installed per channel)
»  DTMF generation function (One block installed per channel. The DTMF signal can be generated by the tone generation function.)
»  2100 Hz single tone/phase inversion detection function (Two blocks installed per channel
»  Tone detection function (400Hz. Detecting frequency can be changed. Two blocks installed per channel
»  Tone generation function (One block installed per channel)
»  FSK generation function (One block installed per channel)
»  Meody generation function (One block installed for every two channels
»  Dial pulse detection function (One block installed per channel.): Secondary function of a general-purpose input/output port
»  Dial pulse transmission function (One block installed per channel): Secondary function of a general-purpose input/output port
»  16-bit timer (One block installed for every two channels.)
»  Equipped with an interface for serial control
»  Allows downloading of DSP firmware
»  General-purpose input/output port:
- 28 ports (some of them have a secondary function)
»  Power supply voltage:
- Digital power supply voltage (DVDD0, 1, 2, 3, 4, 5, 6) : 3.0 to 3.6V
- Analog power supply voltage (AVDD0,1) : 3.0 to 3.6V
»  Master clock frequency:
- 12.288 MHz (crystal resonator/external input)
»  Power down control by hardware or software
»  Package:
- 176-pin plastic LQFP (LQFP176-P-2424-0.50-ZK)