MG74K/75K/76K

MG74K/75K/76K
0.15 µm Customer Structured Arrays

Documents

» PDF of this Data Sheet (296 KB) is available.

MG74K_75K_76K.pdf

Description

Oki’s 0.15 µm Application-Specific Integrated Circuit (ASIC)products are available in Customer Structured Array (CSA)architectures. The CSA-based MG74K/75K/76K series uses a six-layer metal process on 0.15 µm drawn CMOS technology.

The MG74K/75K/76K series uses four, five, and six layer metal, respectively.

The 0.15 µm CSA family provides significant performance, density, and power improvement over previous 0.16 µm technologies. Using an innovative 4-transistor cell structure, the MG74K/75K/76K offers a 30% speed increase, consumes 25% less power, and has 20% higher density than traditional cell designs. The 0.15 µm CSA family operates using 1.5V VDD core with optimized 3.3V I/O and 5V tolerant I/O buffers.The 4-, 5-, and 6-layer metal MG74K/75K/76K series contains 21 base arrays, offering up to 868 I/O pads and over 25M raw gates. These CSA sizes are designed to fit the most popular quad flat pack (QFP), low profile QFPs (LQFPs), thin QFPs (TQFPs), thin fine pitch land grid array (TFLGAs), low pro- file fine pitch ball grid array (LFBGAs), and plastic ball grid array (PBGA)packages.

The MG74K/75K/76K series is ideally suited for memory-intensive ASICs and high volume designs where fine tuning of package size produces significant cost and/or real-estate savings.

Features

»	0.15 µm drawn 4-, 5-, and 6-layer metal CMOS Optimized 1.5V core
»	Optimized 3.3V I/O
»	Optimized 5V Tolerant I/O
»	28-ps typical gate propagation delay (for a 4x- drive inverter gate with a fanout of 2 and 0 mm of wire, operating at 1.5V)
»	Over 25M raw gates and 868 I/O pads using 60 µm staggered I/O
»	User-configurable I/O with V SS, V DD, CMOS, TTL, and 2-to 24-mA options
»	Slew-rate-controlled outputs for low-radiated noise
»	Clock tree cells that reduce the maximum skew for clock signals
»	Low 44 nW/MHz/gate power dissipation
»	User-configurable single-and dual-port memories
»	Specialized IP cores and macrocells including 32-bit ARM CPU,phase-locked loop (PLL), and peripheral component interconnect (PCI) cells
»	Floorplanning for front-end simulation,back- end layout controls, and link to synthesis
»	Joint Test Action Group (JTAG) boundary scan and scan path Automatic Test Pattern Generation (ATPG)
»	Built-in Self Test (BIST) for memory test
»	Support for popular CAE systems including Cadence, Model Technology, Inc.(MTI), and Synopsys