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MG73Q/74Q and MSM98Q/99Q
0.35µm Customer Structured Arrays Data Sheet
 

Documents

»  PDF of this Data Sheet (361 KB) is available. MG73Q-74Q-MSM98Q-99Q.pdf
»  0.35µm Line Card. MSM13Q/14Q

Description

Oki's 0.35µm Application-Specific Integrated Circuit (ASIC) products are available in Customer Structured Array (CSA) architectures with 0.60-µm or 100-µm I/O pad pitch. Both the MG73Q000 and the MSM98Q000 series use a three-layer metal process on 0.35µm drawn (0.27µm L-effective) CMOS technol- ogy. The MG74Q and MSM99Q series uses the same base-array architecture as the MG73Q or MSM99Q series respectively,but offers four metal layers instead of three.The semiconductor process is adapted from Oki's production-proven 64-Mbit DRAM manufacturing process.

The 0.35-µm family provides significant performance, density, and power improvement over previous 0.4 and 0.5µm technologies. The Oki 0.35-µm family operates using 3-V V DD core with optimized 3-V I/O buffers and 3-V I/O buffers that are 5-V tolerant. The MG73Q/74Q series contains 21 array bases, offer- ing up to 868 I/O pads and over 2 M raw gates. The MSM98Q/99Q series contains 18 array bases, offering up to 432 I/O pads and over 1.4M raw gates. These CSA array sizes are designed to fit the most popular quad flat pack (QFP), low profile QFPs (LQFPs), thin QFPs (TQFPs), and plastic ball grid array (PBGA) packages.

The 3-layer-metal MG73Q and MSM98Q and 4-layer-metal MG74Q and MSM99Q CSA series offer a wide span of gate and I/O counts. Oki uses the Artisan Components memory compiler which provides high performance, embedded synchronous single-and dual-port RAM macrocells for CSA designs. As such, the MG73Q/74Q and MSM98Q/99Q series is suited to memory-intensive ASICs and high-volume designs where fine tuning of package size produces significant cost or real-estate savings.

   

Features

»  0.35µm drawn 3-, and 4-layer metal CMOS
»  Optimized 3.3-V core
»  Optimized 3-V I/O and 3-V I/O that is 5-V tolerant
»  0.60-µm and 100-µm I/O pitch
»  CSA architecture
»  77-ps typical gate propagation delay (for a 4xdrive inverter gate with a fan-out of 2 and 0 mm of wire, operating at 3.3 V)
»  Up to 2.0 M raw gates and 868 I/O pads
»  User-configurable I/O with VSS, VDD, TTL, 3-state, and 1- to 24-mA options
»  Slew-rate-controlled outputs for low-radiated noise
»  Clock tree drivers which reduces the maximum skew for clock signals
»  User-configurable single- and dual-port memories
»  Specialized macrocells including: phase-locked loop (PLL), LVDS, pseudo-emitter coupled logic (PECL), and peripheral component interconnect (PCI) cells
»  Floorplanning for front-end simulation, backend layout controls, and link to synthesis
»  Joint Test Action Group (JTAG) boundary scan and scan path Automatic Test Pattern Generation (ATPG)
»  Support for popular CAE systems including Cadence, Exemplar, Gambit, IKOS, Mentor Graphics, Model Technology, Inc.(MTI), Zycad, Synopsys, and VIEWLogic