MG73M/74M/75M

MG73M/74M/75M
0.16µm Customer Structured Arrays

Documents

» PDF of this Data Sheet (274 KB) is available.

MG73M-74M-75M.pdf

»	0.16µm Line Card. MG73M/74M/75M

Description

Oki's 0.16µm Application-Specific Integrated Circuit (ASIC) products are available in Embedded Array (EA) architectures. The EA-based MG73M/74M/75M series uses 0.16µm drawn (0.13µm L-effective) CMOS technology.

The MG73M/74M/75M series uses three, four and five metal, respectively.

The semiconductor process is adapted from Oki's production-proven 64Mbit DRAM manufacturing process.

The 0.16µm EA family provides significant performance, density, and power improvement over previous 0.25µm technologies. An innovative 4-transistor cell structure provides 30% to 50% less power and 30% to 60% more usable gates than traditional cell designs. The 0.16µm EA family operates using 1.8-V VDD core with optimized 3-V I/O buffers. The 3-, 4-, and 5-layer metal MG73M/74M/75M series contains 12 array bases, offering up to 588 I/O pads and over 8.8M raw gates. These EA sizes are designed to fit the most popular quad flat pack (QFP), low profile QFPs (LQFPs), thin QFPs (TQFPs), plastic ball grid array (PBGA), and metal ball grid array (MBGA) packages.

Oki uses the Virage Components memory compiler for EA designs. As such, the MG73M/74M/75M series is suited to memory-intensive ASICs and high volume designs where fine tuning of package size produces significant cost or real-estate savings.

Features

»	0.16µm drawn 3-, 4-, and 5-layer metal CMOS
»	Optimized 1.8V core
»	Optimized 3.3V I/O
»	37-ps typical gate propagation delay (for a 4xdrive inverter gate with a fanout of 2 and 0 mm of wire, operating at 1.8V)
»	Over 12M raw gates and 688 I/O pads using 60µ staggered I/O
»	User-configurable I/O with VSS, VDD, TTL, 3-state, and 1- to 24-mA options
»	Slew-rate-controlled outputs for low-radiated noise
»	Clock tree cells which reduces the maximum skew for clock signals
»	Low 0.1µW/MHz/gate power dissipation
»	User-configurable single- and dual-port memories
»	Specialized IP cores and macrocells including 32-bit ARM CPU, phase-locked loop (PLL), and peripheral component interconnect (PCI) cells
»	Floorplanning for front-end simulation, backend layout controls, and link to synthesis
»	Joint Test Action Group (JTAG) boundary scan and scan path Automatic Test Pattern Generation (ATPG)
»	Built-in Self Test (BIST) for memory test
»	Support for popular CAE systems including Cadence, Model Technology, Inc. (MTI), and Synopsys