Product Information
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General Features

  • Extensive macrocell library including USB 1.1 Device Controller, Ethernet 10/100 MAC, 1-Gigabit Ethernet MAC, ARM920T (32b RISC CPU), ARM946E, ARM926EJS, ARM7TDMI (32b RISC CPU), IEEE1394(Firewire), UART(with FIFO), USB 2.0 Phy, USB 2.0 Device Controller, USB 2.0 Device Controller with AMBA Wrapper, Ethernet 10/100 MAC with AMBA Wrapper
  • Automatic test-pattern generation, with scan flip-flop macrocells, obtaining fault coverage in excess of 95% and scan insertion
  • User-generated models for memory functions
  • Core Voltage: 3.3 V and 5 V operation in 0.5 µm (1st generation & 2nd generation), 2.5 V operation in 0.25 µm, 1.5 V operation in 0.15 µm, 1.2 V operation in 0.13 µm
  • I/O Voltage: 3.3 V/ 5 V operation in 0.5 µm (1st generation), 3.3 V operation in 0.5 µm (2nd generation), 3.3 V operation in 0.35 µm, 3.3 V operation in 0.22 µm, 3.3 V operation in 0.15 µm, 3.3 V and 2.5 V operation in 0.13 µm.
  • Programmable output currents of 1, 2, 4, 6, 8, 12, and 24 mA
  • Configurable I/O cells: Output Macrocells: push pull, 3-state, open drain, slew-rate-controlled output options, Input Macrocells: input buffer LVTTL/LVCMCS levels, input buffer LVTTL/LVCMCS Schmitt levels, Pull up resistor and Pull down resistor. Bi-directional Macrocells: I/O Buffer LVTTL/LVCMCS input levels, I/O Buffer LVTTL/LVCMCS Schmitt input levels. Oscillator: low and medium-frequency oscillator
  • Gated oscillators from 32 kHz to over 55 MHz
Selection Guide

 

 



Family Name More Information Type  1 Process  2 Core Voltage I/O Voltage I/O Signal Delay  3 Raw Gate Range Usable Gate Range I/O Range
MG87J5/6/7/800 SC 0.13µm 5, 6, 7, 8 LM 1.2 V 3.3 V / 2.5 V 5-V Tolerant 19 ps 331K to 37M 244K to 16M 88 to 868
MG74K/75K/76K CSA 0.15µm 4, 5, 6, LM 1.5 V 3.3 V 5-V Tolerant 33 ps 221K to 25M 163K to 10.4M 68 to 868
MG73N/74N/75N  CSA 0.22-µm 3, 4, 5 LM 2.5 V 3.3 V 5-V Tolerant 50 ps 44K to 9.3M 36K to 3.9M 68 to 868
MG33Q/34Q SOG 0.35-µm 3, 4 LM 3.3 V 3.3 V 5-V Tolerant 62 ps 28K to 346K 24K to 280K 108 to 348
MG73Q/34Q  CSA 0.35-µm 3, 4 LM 3.3 V 3.3 V 5-V Tolerant 77 ps 9K to 2M 6K to 904K 68 to 868
MSM12R/ 13R SOG 0.5-µm 2, 3 LM 3.3 V 3.3 V 5-V Tolerant 70 ps 17K to 500K 8K to 270K 104 to 504
MSM32R/ 30R SOG 0.5-µm 2, 3 LM 3.3 V 3.3 V 5-V Tolerant 80 ps 14K to 306K 7K to 174K 80 to 320
MSM92R CSA 0.5-µm 3 LM 3.3 V 3.3 V 5-V Tolerant 80 ps 14K to 1.1M 11K to 500K 80 to 600
MSM98R CSA 0.5-µm 3 LM 3.3 V 3.3 V 5-V 70 ps 14K to 714K 11K to 357K 96 to 600
MG38R SOG 0.5-µm 3 LM 5 V 5 V 5-V 90 ps 13K to 176K 10K to 105K 180 to 256
 
1. SC = Standard Cell. CSA = Customer Structured Array. SOG = Sea of Gates Array.  SOGs use predefined diffusion patterns and are available in a smaller range of sizes. CSAs use a predefined layout frame size but allow diffusion-level (all mask level) customization of the array. SC are pre-characterized function cells allowing for hierarchical design and smaller die size but at the cost of longer design cycle.
2. Drawn geometries (effective geometries are smaller). LM = Layers of Metal.
3. Internal gate propagation delays are quoted for a 4x-drive inverter driving two outputs and 0 mm of wire.