µPLAT™ GPIOtest
Application Note
 

Documents

Description

The purpose of this application note is to describe the functions and usage of the GPIOtest program. In the GPIOtest program, three main files used to build an executable image. The listings of these three files are included in this application note. The three files, along with the project file for the GPIOtest program, are available in a zip file (GPIOtest.zip) that can be downloaded from the Oki web site: http://okisemi.com.

Related documentation for the µPLAT Prototyping board can be found at: http://www2.okisemi.com/site/support/Documents.html.

The purpose of the GPIOtest program is to provide the new user of the µPLAT Prototyping board with a tested and debugged executable program. This program facilitates operation of the many features available on the µPLAT Prototyping board. Building the executable image for this program and executing it on the µPLAT Prototyping board will provide a high degree of confidence that the board and the ARM Software Development Toolkit (SDT) are correctly installed and working correctly.

The µPLAT Prototyping board includes a 16-bit General Purpose Input Output (GPIO) port as a soft IP (intellectual property). Each bit of the port can be configured as an input or an output using Control registers. If configured as an output, a latch holds the high or low logic level last set to the port.

The GPIO port is designed as an Advanced Peripheral Bus (APB) block, so it's correct operation verifies the two FPGA devices on the µPLAT Prototyping board and the ML670000 EVA chip containing the µPLAT-7C core. This verification occurs because the ML670000 EVA chip uses the Advanced Microcontroller Bus Architecture (AMBA) standard for peripheral blocks. The first FPGA contains the Advanced High-Performance Bus (AHB) to APB interface block. The second FPGA contains the APB block and the GPIO port.

The GPIOtest program provides a feature that allows it to copy itself into the FLASH memory on the µPLAT Prototyping board. After the copy into FLASH memory is completed, the board can remain under host control, or can be disconnected from the host computer and operated in stand-alone mode. When operating under control of the ARM debugger and a JTAG protocol converter such as the Oki ADI board, the FLASH memory can also be tested. The SRAM memory can be tested in either the stand-alone mode or the debugger-hosted mode.

The GPIOtest program uses the DIP switches connected to the GPIO port to select which test to perform. The LEDs connected to the GPIO port are used to display the results of a test or the general status of program operation. The 16-bit timer, part of the µPLAT-7C core, is used for switch de-bouncing and timing of the LED display rate.