ARM7TDMI-Based Integration Platform Data Sheet
Documents
| » PDF of this Data Sheet (1173 KB) is
available. |
UPLAT-7C.pdf
|
Related Documents
Description
The
µPLAT ™-7c is a 0.25µm integration platform incorporating an ARM7TDMI ™-based
sub-system to implement system-on-a-chip designs. The µPLAT ™-7c re-usable IP
core combines a 32-bit ARM7TDMI ™ RISC CPU, unified cache memory, peripheral
support functions, and AMBA ™ Advanced High-Speed Bus (AHB)interface. The µPLAT
™-7c supports a wide range of off-chip or on-chip memories, and provides
high-performance operation using its 8k unified cache to implement high
performance ASIC designs.
Features
| » |
0.25-µm CMOS (three metal layer) process |
| » |
100 MHz operation @ 2.5 V, Tj=25°C, typical process |
| » |
ARM7TDMI™ 32-bit RISC CPU (54 MIPS @60 MHz) |
| » |
2.1 mA/MHz @ 2.75 V power consumption |
| » |
2.25 to 2.75 V power supply operation |
| » |
Little Endian support |
| » |
Cache memory system
| » |
8 kByte unified cache |
| » |
4-way set associative, controlled by pseudo-Least Recently
Used (pLRU)algorithm |
| » |
Write back |
| » |
Non blocking | |
| » |
Internal AMBA™ AHB bus interface |
| » |
16-bit timer for operating system use |
| » |
Serial interface supports start-stop transfers |
| » |
External Memory Controller
| » |
Memory and I/O space are bank-addressed |
| » |
Each bank is a 128 MB space |
| » |
Bank width is 8/16/32 bit device-selectable. |
| » |
Page mode ROM or Flash control memory space |
| » |
Page mode Flash or SRAM control memory space |
| » |
SDRAM |
| » |
IO space | |
| » |
Interrupt Controller
| » |
Connected to ARM7TDMI" IRQ |
| » |
Dedicated UART and timer interrupts |
| » |
14 non-dedicated inputs available (expandable to 126 plus the
two dedicated inputs) | |
| » |
Test Interface Controller in accordance with ARM™ test logic
|
| » |
Power control
| » |
Individual module control, via software |
| » |
Entire core powerdown, via HW or SW
| |
|
|
|
privacy policy