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ML67Q4050 Series  ML67Q4050/Q4051 32-Bit
ARM®-Based General Purpose Microcontrollers
Documents
Description
 The Oki ML67Q4050 Series of Advantage
Microcontrollers contains a 33.333-MHz, 32-bit ARM7TDMITM core with
either 64 or 128KBytes of 32-bit wide zero-wait state FLASH memory and 16KBytes
of SRAM. The devices also contain multiple serial interfaces, like
I2C, I2S, SPI, and UARTs (supporting 9-bit
communications), along with many other peripheral functions.
Features
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ARM7TDMITM CPU
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Internal Memory
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64KB or 128KB 32-bit wide FLASH, zero wait state |
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16KBytes SRAM |
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Boot loader | |
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External Memory Controller
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ROM, RAM and I/O banks |
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8, 16 or 32-bit wide accesses
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Power Supply
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2.5V VDD_CORE |
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Selectable 2.5V to 3.3V VDD_IO
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Programmable Timers
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16-bit System Timer |
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Six 16-bit Flexible Timers |
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Auto reload, input capture, output compare
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16-bit Watchdog timer
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Selectable interrupt or
reset | |
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Two DMAC Channels |
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Four 10-bit A/D converter channels |
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Two UART channels
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16550A-compatible |
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Independent 16-bit Tx and Rx FIFOs |
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Supports 9-bit mode | |
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I2C
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Conforms to I2C bus specification Ver-2.1 |
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Multi-master support | |
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SIO
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Full duplex operation with built in baud rate
generator | |
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I2S
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Conforms to the I2S (the Inter-IC Sound)
specification for DAC/ADC IF |
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Supports master/slave modes |
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Channel data length 16/18/20/24-bit (CPU interface is 16 bits)
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One 256 x 16 shared FIFO |
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Master clock output | |
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Two SPI channels
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Selectable master/slave |
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Independent 16 entry x 16-bit FIFOs |
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Supports 8-bit and 16-bit transfers
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Clocks
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Main clock (16 MHz - 33.333 MHz) |
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RTC clock (32.768 kHz) |
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Ring Oscillator | |
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Power Management
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Low-power mode |
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Halt mode |
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Stop Mode |
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Clock divider can be dynamically changed during
operation | |
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Package
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Applications
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Consumer, medical, and communications applications where small
package size is
important. | |