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ASIC CSP Solutions
Oki offers a range of technologies from 0.15µm to 0.5µm along with a wide
choice of IPs, and ARM7TDMI, ARM920T, and ARM946E-88 cores. Customers can choose
Sea-of-Gates (SOG), Customer Structured Arrays (CSA) or Standard Cells (SC).
Using Oki's CAD S/W, the SOG transistors (area) can be removed and replaced by a
diffused memory or mega cell(s) based on customer's specifications. Standard
Cell (SC architecture/macrocells can be combined with the CSA architecture for
critical path oriented designs)
Additional Features
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Oki's advanced CAD tools (Synopsis, Cadence and more)
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Floor planning, JTAG, clock skew, power calculation, physical
synthesis, and scan insertion tools for first time success |
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GGT placement tool that reduces clock wire capacitance up to
30% |
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Automatic test pattern generation with scan flip-flop
macrocells which obtain fault coverage in excess of 95 percent and scan
insertion |
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Experienced engineering team to convert FPGA-ASIC. Oki's team
has completed over 100 conversions. |
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Wide range of packages including industry leading Wafer-Level
Chip Size Packaging (W-CSP) for low- power, small form factor applications
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for ASICs/SOC section.
µPLAT™ Prototype Board
CSP Solutions |
