Product Information


Timing generation

Q1. Are all the MTIE Stratum4E specifications met, including the intrinsic jitter, for the local clocks?
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Q2. My H.100 test system has several identical signaling cards, each using a CTx12. They are configured so that one is acting as Primary Master (clock set A), another Secondary Master (clock set B, auto changeover to Primary Master if clocks fail) and the third as a slave (Using clock set A, auto-changeover to alternate valid clock set if current fails). If the board acting as Primary Master is made a Slave then the Secondary Master becomes a Primary Master as expected, and the Slave switches to use the other clock set. A jitter analyzer is connected to the Slave board and recovering clock. This equipment measures more jitter than I would expect, and a scope on clock B shows the clock briefly but visibly dying away while the changeover occurs before returning again. Is there a setting in the CTx12 that allows reducing the jitter?
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Q3. Are the CTx12 compliant with the European Specs of CTR4, CTR12 and CTR13 for jitter?
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Q4. Do you have any real data for the jitter transfer functions and intrinsic jitter measurements?
No data exists. ...more
Q5. At what frequency is the pole situated for the jitter transfer function?
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Q6. How is the jitter transfer function affected by which frequency input (8Khz, 1.544Mhz, 2.048Mhz) is selected?
It is not affected. ...more
Q7. What is the maximum skew between local clocks 1 and 2?
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Q8. When using multiple devices on the same board, can
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Q9. What is the Holdover mode in the master PLL? Is this procedure compliant to the H.110 requirement (section 2.3 and 2.4) for Stratum 4E?
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Q10. What is the intended use of separated local clocks (L_CLK_0 and L_CLK_1) and local frame sync (L_FS_0 and L_FS_1)?
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Q11. What clock (L_CLK) and frame sync (L_FS) should be used for the local bus data streams?
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Q12. Can these pins be used as inputs?
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Q13. Can the Jitter Attenuation feature be disabled?
No. ...more
Q14. How much time is accumulated in the holdover mode?
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Q15. How does the Master PLL detect a failure?
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Q16. Must the local bus signals L_CLK_0/1 and L_FS_0/1 be synchronized with the CT Bus signals CT_C8_A/B and CT_FRAME_A/B_N?
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Q17. When L_CLK0 is configured to operate at 16.384MHz, what is the maximum jitter the signal can have?
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Q18. What happens when the master clock comes after the slave clock has been running? Is there a glitch on the clock or is it a smooth transition?
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Q19. Looking at the Configuration register byte 9 and 10, the minimum input frequency for L_CLK is 2.048Mhz. Is that only for E1? What about T1 at 1.544 MHz?
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Q20. Do you have any jitter measurement available for the devices?
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Q21. I'm running the CTx12 device as a CT Bus Slave, and I see a single instance of an extra half frame of clocks as my system is booting up. This is seen on the L_FS output when I lose timing on CT_C8 and CT_FRAME_N signals. Is there anyway to configure the Slave PLL to prevent this?
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