It might be possible to run the APLL_CLKREF at 16.388 MHz, but we don't recommend it. 16.388 MHz is 244 ppm (4/16384) away from the ideal center frequency, plus you have to add the tolerance of the oscillator to that number. The master digital PLL can lock to a range of 488 ppm, so it's getting close (jitter on the network reference also reduces lock range). Typically, the APLL_CLKREF signal is within 25 or 32 ppm of ideal, and this allows the clock master to free run within the tolerance of most network specifications. If this was a slave only application, then 16.388 MHz would probably be OK.