Why does the JTAG interface to the ML67Q4003 CPU board fail to establish a connection to the EmbeddedICE?
Descriptive Answer:
Problem Description: When interfacing to an ML67Q4003 CPU board using standard JTAG-debugger interface units, JTAG errors are observed and as a result a JTAG connection cannot be established. Errors such as "JTAG not initialized" or "Could not stop processor" are noted. These errors may arise even though the user has been able to successfully connect via the same JTAG debugger interface unit to other Oki CPU boards.
Solution:
The early versions of ML67Q4003 CPU boards use an adaptive clocking circuit to synchronize the JTAG port. This JTAG circuit design is different from previous implementations on Oki ARM CPU boards.
To be able to interface to ML67Q4003 CPU board through JTAG, the user must configure their JTAG-Debugger Interface Unit (e.g. MultiICE) to use adaptive clocking.
Adaptive clocking is the method to synchronize all JTAG operations on a single clock edge. This may be necessary for various types of applications. In JTAG operation, the JTAG clock (TCK) is supplied by the JTAG-debugger interface unit. When adaptive clocking is utilized, the JTAG-debugger interface unit will issue a JTAG clock (TCK) and check for a return clock (RTCK) from the ARM MCU before issuing the next clock tick (TCK).
This concept is very useful in interfacing to systems which have widely varying clock frequencies. For example, in battery-operated operations, the application may utilize the flexible clock gears of ML674K MCUs to vary processor clock frequency based on processing needs of the system. In this type of application where the core clock frequency may frequently vary, the JTAG clock can be several times faster than the core frequency. Thus, adaptive clocking is used and insures that the JTAG-debugger interface unit adapts its clock frequency to the target system.
The figure below illustrates how the clocking circuit for the JTAG embedded-ICE of ML67Q4003 has been modified to generate the RTCK adaptive return clock (interfacing buffers are not shown).
Solution:
The early versions of ML67Q4003 CPU boards use an adaptive clocking circuit to synchronize the JTAG port. This JTAG circuit design is different from previous implementations on Oki ARM CPU boards.
To be able to interface to ML67Q4003 CPU board through JTAG, the user must configure their JTAG-Debugger Interface Unit (e.g. MultiICE) to use adaptive clocking.
Adaptive clocking is the method to synchronize all JTAG operations on a single clock edge. This may be necessary for various types of applications. In JTAG operation, the JTAG clock (TCK) is supplied by the JTAG-debugger interface unit. When adaptive clocking is utilized, the JTAG-debugger interface unit will issue a JTAG clock (TCK) and check for a return clock (RTCK) from the ARM MCU before issuing the next clock tick (TCK).
This concept is very useful in interfacing to systems which have widely varying clock frequencies. For example, in battery-operated operations, the application may utilize the flexible clock gears of ML674K MCUs to vary processor clock frequency based on processing needs of the system. In this type of application where the core clock frequency may frequently vary, the JTAG clock can be several times faster than the core frequency. Thus, adaptive clocking is used and insures that the JTAG-debugger interface unit adapts its clock frequency to the target system.
The figure below illustrates how the clocking circuit for the JTAG embedded-ICE of ML67Q4003 has been modified to generate the RTCK adaptive return clock (interfacing buffers are not shown).
Therefore, to interface to ML67Q4003 CPU boards, the user has the following options:
| » | Configure the JTAG-debugger interface unit used to accept adaptive clocking. For example, with ARM Multi-ICE, adaptive clocking can be set in the Settings menu of the Multi-ICE server. |
If the JTAG-debugger interface unit at hand does not support adaptive clocking:
| » | Slow down the JTAG clock of the JTAG-debugger interface unit, until a JTAG connection can be established. This method works because, if the JTAG clock is slowed down significantly, even if RTCK is not being sensed, the TCK will have been slowed down enough that it is always lagging RTCK and therefore detection of RTCK becomes irrelevant. |
