Oki's ARM-based MCUs have a separate reset pin for the MCU system (RESET_N) and for the on-chip debug unit (nTRST). This feature allows flexibility during JTAG debugging. The on-chip hardware debug unit in every Oki ARM MCU enables debugging through JTAG. When the on-chip debug unit's reset signal (nTRST) is asserted, the communication through the JTAG-debugger interface (TAP) is temporarily interrupted and any hardware breakpoints set will be lost. For a flexible debug architecture, it is necessary to have separate reset lines for the on-chip debug unit so that when the MCU system reset (RESET_N) is asserted the ICE unit does not get reset and continues to remain in control of the debug interface.

Some ARM MCU vendors multiplex the two resets into one signal. In this scenario, when the MCU system reset is asserted, the on-chip debug unit gets reset as well. This creates problems during debugging, since the debug state is altered by this reset and the debugger must re-initialize and reopen the debug channel after the reset. In this scenario, debuggers cannot gain control of the chip immediately after reset causing issues such as memory corruption or inconveniences during debugging.

When designing the Oki ARM MCU circuit, if the JTAG interface is to be used for debugging, the designer should connect the nSRST signal from the JTAG header to the system reset (RESET_N) of the Oki MCU and the JTAG reset signal (nTRST) to the nTRST pin on the Oki MCU. For recommended sample circuits, refer to the JTAG chapter of Oki's ARM MCU User's Manual.

Many ARM debuggers have the feature to assert reset to the target from inside the debugger on the host development system. This reset feature can usually be configured to either assert nTRST (JTAG Reset), or nSRST (System Reset), or both at the same time. The user should appropriately configure this feature.