How are the chip select addressing on the I/O banks of ML674K MCUs divided?
Descriptive Answer:
ML674001/2/3 MCUs each have 4 I/O banks. Each I/O bank has its own chip select. The chip select addressing is pre-defined and thus it is not programmable. The break down of chip select addresses of the I/O banks is as follows:
0xF000,0000-0xF1FF,FFFF XIOCS0
0xF200,0000-0xF3FF,FFFF XIOCS1
0xF400,0000-0xF5FF,FFFF XIOCS2
0xF600,0000-0xF7FF,FFFF XIOCS3
0xF000,0000-0xF1FF,FFFF XIOCS0
0xF200,0000-0xF3FF,FFFF XIOCS1
0xF400,0000-0xF5FF,FFFF XIOCS2
0xF600,0000-0xF7FF,FFFF XIOCS3
